1. Field of the Invention
The present invention relates to a semiconductor integrated device. In particular, the present invention relates to a semiconductor integrated device in which damage to circuits under pads at the time of wafer test and the occurrence rate of cracks in circuits under pads are reduced without detriment to wire bonding characteristics.
2. Description of the Prior Art
In recent years, it has been well known that information electronic equipment comprises semiconductor integrated devices which contain transistors. As shown in FIG. 1, a semiconductor chip 101 of the semiconductor integrated device has an internal circuit area 102 which contains transistors, and I/O buffers 103 on the periphery of the semiconductor chip 101. The I/O buffers 103 are configured to connect the internal circuit area 102 and external devices. The semiconductor chip 101 further has pads 104 connected to the I/O buffers 103 by interconnection lines 105. In particular, in the case where the semiconductor chip 101 is large in size, the semiconductor chip 101 has many I/O buffers 103.
Moreover, in a semiconductor integrated device of this type, it has been also known that the manufacturing yield of the semiconductor integrated device is improved by reducing the area occupied by a chip. Specifically, as shown in FIG. 2, in a semiconductor chip 201 of this type, pads 204 are arranged in I/O buffers 203 in order to reduce the area occupied by a chip.
Moreover, it has been also publicly known that a two-metal-layer structure is adopted as the structure of the pad 204. The pad 204 has a multilayer structure in upper and lower sides of which have two ore more layers of conductive films which are connected by a plurality of conductive plugs. Such a conductive pad having two or more layers in upper and lower sides therein is disclosed in, for example, Japanese Patent Laid-Open Publication No. 2001-358169.
FIG. 3A depicts a plan view of an I/O buffer 300 containing the conventional pad of the above described structure. FIG. 3B depicts a cross-sectional view taken along the line Ixe2x80x94I in FIG. 3A.
The conventional I/O buffer 300 has a semiconductor substrate 304 and a semiconductor device 312 formed on the semiconductor substrate 304. The conventional I/O buffer 300 further has insulating films (305-1, 305-2, and 307) in a plurality of layers and conductive films (306-1 and 306-2) in a plurality of layers, both of which are formed on the semiconductor device 312.
Furthermore, the conventional I/O buffer 300 has a pad 314 comprising a conductive pad 301 in an upper layer, a conductive pad 308 in a lower layer, and conductive plugs 311 which connect the conductive pads (301 and 308) in the upper and lower two layers. Moreover, the conventional I/O buffer 300 has an insulating film 309 disposed in the uppermost layer.
Here, in the plan view of FIG. 3A, the conductive plugs 311 are depicted as if they can be seen, for convenience of explanation, though they cannot be seen due to the conductive pad 301 actually. Moreover, the conductive films (306-1 and 306-2) are also depicted as if they can be seen, for convenience of explanation.
In the pad 314, the conductive pad 308 in the lower layer is formed on an interlayer insulating film 307, and furthermore, the conductive pad 301 in the upper layer is formed thereon with an interlayer insulating film 309 interposed therebetween. An interconnection line 308a to be connected to an internal circuit is led from the conductive pad 308 in the lower layer. The conductive pad 308 in the lower layer and the conductive pad 301 in the upper layer are connected by the plurality of conductive plugs 311. Here, the conductive plugs 311 are arranged in the form of a square grid over the entire surfaces of the conductive pads at the minimum spacing specified by a design standard, or at approximately the minimum spacing.
Note that technologies for arranging conductive pads in a plurality of layers and connecting the conductive pads using conductive plugs have been publicly known by, for example, Japanese Patent Laid-Open Publication No. 2000-114309 and the like.
In the conventional semiconductor chip 201 described above, after a manufacturing process in a wafer state has been completed, the pads 314 are explored with probes for testing. Moreover, after the semiconductor chip 201 has been separated into each individual chip and die-bonded to an island of a package, wires are bonded to the pads 314. Probing is performed on the pads obliquely from above. Further, at the time of wire bonding, ultrasonic vibration is applied to a tool.
However, in the pad structure of FIG. 3A, cracks are apt to occur under the pads due to stress during probing or wire bonding. A wafer test and wire bonding with these pads 314 having a two-metal-layer structure cause considerable damage to conductive films, insulating films, and circuit devices arranged under the pads. On the other hand, if a single-metal-layer structure is adopted in order to avoid damage, pads tend to be peeled off. This causes deterioration in bonding characteristics.
Accordingly, an object of the present invention is to provide a semiconductor integrated device in which damage to circuits under pads at the time of a wafer test and the occurrence rate of cracks in circuits under pads can be reduced without detriment to wire bonding characteristics in a layout structure in which circuits exist under pads (such a layout structure is referred to as xe2x80x9cCircuit Under Padxe2x80x9d and hereinafter abbreviated to CUP).
A semiconductor integrated device of the present invention includes a first insulating film and a second insulating film formed on any one of a conductive layer and an interlayer insulating film, a lower layer pad of a two-layer pad formed on the first insulating film, a third insulating film deposited on both of the first insulating film and the lower layer pad of the two-layer pad, a conductive plug which to connects upper and lower pads of the two-layer pad and which is formed in the third insulating film, a upper layer pad which is in the two-layer pad and which is formed on the third insulating film, a second insulating film which is formed on any one of the conductive layer and the interlayer insulating film and which has a film thickness greater than that of the first insulating film, and a single-layer pad formed on the second insulating film.
The single-layer pad is bonded without a bonding wire, and the second layer pad of the two-layer pad is bonded with the bonding wire.